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Limit Overload for design


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I have found a possible bug in PVsyst v6: editing the Hidden PVsyst parameter, I have changed the value of "Limit overload loss for design" to a 5% value (default value for this parameter is 3%), as I did before in PVsyst v5. When I'm trying to simulate with an overload value over 3%, the following message is shown: "The inverter power is strongly undersized". The bug is that if I close PVsyst and run it again, the value of "Limit overload loss for design" has come back to 3% again, and other values are never taken into account, so I can not simulate my PV plant if this value is exceeded.

Kind regards.

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This is the parameter I am talking about:


I have tried to reinstall the software, but the problem persists and whatever introduced value is not taken into account.

Finally, I have observed that if I change the value, exit PVsyst and open PVsyst again, the value is saved and everything it's ok. :shock:

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  • 3 weeks later...

For me, it's a problem.

Because I could not run simulation. And I could not find the place to change the setup.

But still thanks, the forum help me to solve it that I could run simulation.

I don't whether in the help book there is an introduction to this setup, I did search the help book but I didn't find it.

If not suggest to add it.

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When you are in the project's definition dialog, you have a button "Albedo-Settings"

Pushing this button you have the item "Limit overload loss for design".

This defines the amount of overload energy you accept to loose over the year.

The help is available from anywhere in the software, by typing F1 (or sometimes little orange questionmarks for more targeted answers).

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  • 1 month later...

This conversation has been most helpful for me in clearing up that confusion.

However, the issue I am now having is that the Limit Overload Loss for Design in the Hidden Parameters changes back to 3% every time I restart PVsyst V6.12 . Any thoughts on why this is?


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