In the LID input from the detailed losses, The LID loss[%] is loss from the nameplate power(which does not include power tolerance), or loss from actual flash data(which does include power tolerance)? Nameplate power does not include the power tolerance(usually up to +3% or +5W), and the actual flash data includes the power tolerance. I can see a separate input, module quality loss to consider power tolerance from the nameplate power. So LID input in PVsyst is the loss from the nameplate power, or the loss from the actual flash data? Thank you.