Oversized Arrays Preventing Simulations Being Enabled

[njetherington]

I've not seen or figured out how to get around a situation (using PVsyst 5.68 and PVsyst 6.10) where an array sized at 1.4:1.0 cannot be simulated. Initially I had the problem only with version 6 but it appears that my Version 5 cannot run at the level of oversizing I wish to explore. Please explain whether this is user error or a software configuration or just a bug.

Thanks, Nigel

[André Mermoud]

You have to change the parameter "Limit Overload Loss for Design".

In the version 5, in the Hidden parameters "Detailed Simulation Verification Conditions".

In the version 6, in the Project's parameters, button "Albedo-Settings".

In the FAQ, please see "Can I define a system with very oversized Inverter ? "

[njetherington]

Thanks. Problem solved! :roll:

Nigel