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 Post subject: What is the LID loss ?
PostPosted: Wed Jul 13, 2016 6:02 pm 
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Joined: Mon Apr 16, 2012 7:29 pm
Posts: 1686
The LID loss ("Light Induced Degradation") is a phenomenon specific to Crystalline modules (and only with P-type bulk wafers). It is due to the wafer quality, namely traces of oxygen, which recombine with doping atoms during the first hours of exposition. It is not taken into account in the flash-test at the output of the factory, and therefore in the sorting process. Therefore it has to be taken into account in the simulation.

The LID loss is sometimes specified in the datasheets, but not very often. When applicable (crysrtalline modules with P-type wafers) the usual value is around 2%, this is the default in PVsyst.
Now in PVsyst, you have to define the LID loss explicitely in the "Detailed Losses" dialog. You can choose the value of your PV module if it is specified with the PAN file, or you can ask for the default value.

The thin film modules (especially amorphous, but also CdTe to a lower extent) are known to degrade during the 2-3 first months. The "sold" nominal power is indeed the STC performance after stabilization. Therefore there is no additional loss with reaspect to the one-diode model during the simulation.
NB: The "gain" before stabilization is not acounted in the simulation, as it is considered as a temporary behavior.

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