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Inverter Loss due to Voltage thershold
https://forum.pvsyst.com/viewtopic.php?f=25&t=5461
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Author:  ACERENEWTECH [ Mon Jul 19, 2021 11:21 am ]
Post subject:  Inverter Loss due to Voltage thershold

Inverter Loss due to Voltage thershold ( i.e. when the array mpp voltage is below VmppMin).
I have run the simulation in PVsyst version 7.1. with Renesola 335 Wp and TMIEC 2.5 MW Inverter for a project. I am getting an Inverter Loss due to Voltage thershold as -8.44%. However my array Vmpp is greater than Inverter Vmin. I have run the same project with same design in PVsyst version 6.84 in which loss dur to Voltage thershhold is 0.00%.

What is the reason behind the changes?

Could you please clarify the same ASAP.

I have mailed the project files to support@pvsyst.com

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