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PostPosted: Fri Feb 02, 2018 2:25 pm 

Joined: Thu Mar 17, 2016 7:49 pm
Posts: 7
Dear Andre,

Why the designing criteria, on the "System" window, does not consider the inverter maximum input current as a restriction, warning when the total array short circuit current is higher then the inverter DC current? Isn´t that should be consider a problem in the design?

Thank you in advance

PostPosted: Fri Mar 02, 2018 7:06 pm 
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Joined: Mon Apr 16, 2012 7:29 pm
Posts: 1493
There are 2 input current limitations in PVsyst:

- At the sizing time: some manufacturers specify a maximum ISC current (or sometimes a maximum PV power) for the array to be connected on the inverter. To my understanding, this doesn't make much sense as the inverter is normally able to limit the input current (or power) by itself.
The only cases where this should be respected are when this is a contractual condition, which affects the warranty. This will provide an error message, and the prohect cannot be created as such.

- During operation, up to now there was a input parameter of the inverter "Minimum Voltage for getting Pnom". This corresponds indeed to an input current limiting, managed by the inverter.
Since recent versions of PVsyst, this current limit may also be explicitly defined, alternatively to VminPnom. These 2 varialbes are closely related: Imax * VminPnom = Pnom !

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