André Mermoud Posted November 6, 2012 Posted November 6, 2012 Module Quality LossThe Module quality loss is a parameter that should express your own confidence to the real module's performance, with respect to the manufacturer's specifications.It is at your entire disposal: you can put here any value (for example for keeping some reserve on the production warranty, or for somelong-term losses, etc). You can also put a negative value (corresponding to a gain) if you want to take the positive sorting into account.By default, PVsyst initializes the "Module Quality Loss" according to the PV module manufacturer's tolerance specification: PVsyst will choose a quarter of the difference between the lower and higher value. For example, with -3..+3%, it will be 1.5%, and with positive sorting 0..+3%, it will be -0.75% (i.e. a gain).NB: This value of a quarter between low and high tolerance is our own choice. We usually consider a conservative option (i.e. the modules will never be better than announced). I doesn't have any other background reasons.LID LossThe LID (Light Induced Degradation) loss appears in the first hours of the exposition to the sun. It is due to the quality of the si-Crystal, only for p-type wafer cells (i.e. traces of oxygen which recombine with doping centers). The one-diode model in PVsyst is based on the STC of the datasheets. You can apply a LID loss afterwards, in the "detailed Losses".By default in PVsyst, the LID losses are ignored (null), you should specify them explicitly in the "Detailed losses". It is not possible to set an "automatic" reasonable value, because some modules are not subject to the LID. On the other hand, PVsyst doesn't automatically put the manufacturer's value, as few manufacturers specify this value, so that they would be penalized.NB: At the output of the factory, the modules are sorted according to their effective (measured) STC values, and attributed to the corresponding Power class. Therefore the STC real values of the modules is accounted before LID.
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